DMA Configuration Bugs and Cache Coherency on Cortex-M7
Cortex-M7 cache incoherence breaks DMA transfers when porting from M4.
Vera Bauer
Contributing Editor
Vera Bauer
Vera Bauer is a contributing editor at Firmware Dispatch covering performance optimization. Based in Buenos Aires, Vera has written for Firmware Dispatch since 2016.
1 story · Buenos Aires